This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2001-392571, filed Dec. 25, 2001, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor device having a patterned SOI (Silicon On Insulator) structure and a method for fabricating the semiconductor device. More specifically, the invention relates to a technique for use in a system LSI using an SOI substrate.
2. Description of the Related Art
Today we enter the broadband age in accordance with the development of computer and networks. In order to process a large amount of data on a network, a variety of semiconductor devices have to be integrated on an LSI at high densities. A try to use SOI in such an LSI requiring a high degree of integration is made. The SOI has conventionally been known widely as a structure in which a silicon layer is formed on an insulation film. Semiconductor elements (SOI elements) formed on the SOI are low in parasitic capacitance and can operate at high speed. It is thus expected that a higher-performance LSI will be achieved by the use of SOI elements.
For example, a system LSI embedded a DRAM (Dynamic Random Access Memory) using SOI elements is proposed by R. Hannon et al., xe2x80x9c0.25 xcexcm Merged Bulk DRAM and SOI logic using Patterned SOI,xe2x80x9d 2000 Symposium on VLSI Technology Digest of Technical Papers.
Whether the use of SOI elements in a system LSI is good or not varies from circuit to circuit contained in the system LSI. It is not desirable to use an SOI element at least in the DRAM cell. This is because the SOI element has a floating body effect inherent therein. It is therefore desirable to form a DRAM cell of non-SOI elements and form other logic circuits, which perform a digital operation, of SOI elements. More specifically, SOI regions are partially formed on a silicon substrate. This structure is referred to as a patterned SOI structure. It is desirable to form a DRAM cell in a non-SOI region (bulk region) and form a peripheral circuit in an SOI region.
A method for fabricating the above patterned SOI structure will now be described with reference to FIGS. 1A to 1D. FIGS. 1A to 1D are cross-sectional views showing steps of fabricating the SOI structure in sequence.
As shown in FIG. 1A, a silicon oxide film 240 is formed on an SOI substrate 300. The SOI substrate 300 includes a silicon substrate 200, a BOX (Buried Oxide) layer 210, and an SOI layer 220. Resist 250 is applied onto the silicon oxide film 240 and then left only on the region that is to serve as an SOI region. As shown in FIG. 1B, the silicon oxide film 240, SOI layer 220, and BOX layer 210 in the bulk region are etched using the resist 250 as a mask to thereby expose the silicon substrate 200. After that, the resist 250 is removed. As illustrated in FIG. 1C, a silicon layer 230 is selectively formed on the silicon substrate 200 by epitaxial growth. Since the silicon oxide film 240 is exposed in the SOI region, the silicon layer 230 grows only on the silicon substrate 200 in the bulk region. As shown in FIG. 1D, the silicon oxide film 240 remaining in the SOI region is removed.
The above-described method can create a patterned SOI structure in which SOI partially exists on the silicon substrate. After that, for example, a logic circuit is formed on the SOI layer 220 in the SOI region. Further, for example, a DRAM cell is formed on the silicon layer 230 in the bulk region. The SOI and non-SOI elements are used selectively according to the characteristic of semiconductor elements, with the result that a high-speed, high-performance system LSI can be achieved.
In the foregoing fabricating method, however, it was sometimes very difficult to measure the thickness of the silicon layer 230 formed in the bulk region.
The deposition rates in a deposition step of a semiconductor fabricating process are not always the same even though the deposition conditions are set to the same. It is rather usual that the deposition rates vary even though the deposition conditions are the same. This is caused by subtle change of external environment (temperature, pressure, humidity) and internal environment (state of inside of chamber, state of sensor), the surface state of a semiconductor wafer, and the like while a deposition device is operating. Consequently, the deposition rate (film thickness) of the deposition conditions needs to be measured. The deposition conditions need to be optimized by feeding the measurement result back to the deposition conditions of the next deposition. Especially in an SoC (System on Chip) type high-performance system LSI, thickness control is very important in increasing the accuracy of photolithography process. For example, in the patterned SOI structure, it is desirable to reduce a difference in level between the bulk and SOI regions as much as possible. In other words, the growth conditions of the silicon layer 230 have to be controlled such that the top surface of the silicon layer 230 in the bulk region and that of the SOI layer 220 in the SOI region are flush with each other. To do this, the thickness depi of the silicon layer 230 should be measured. Naturally, the thickness is measured by non-destructive inspection in order to improve yields. For example, an optical method using light reflected by the boundary between respective layers is employed.
In the patterned SOI structure shown in FIG. 1D, however, the silicon layer 230 whose thickness is to be measured is made of the same material as that of the underlying substrate 200. In other words, there is hardly a difference in optical constant between them. It was therefore very difficult to measure the thickness of the silicon layer 230. Consequently, the result of deposition obtained under the deposition conditions could not be reflected in its subsequent deposition; thus, there was a case where the fabricating yields of the system LSI decreased.
A semiconductor device according to an aspect of the present invention comprises:
a first semiconductor layer formed in a first region of a semiconductor substrate;
a second semiconductor layer formed in a second region of the semiconductor substrate with an insulation film interposed between the semiconductor substrate and the second semiconductor layer; and
a third semiconductor layer formed in a third region of the semiconductor substrate with the insulation film and a part of the second semiconductor layer extending in the third region and interposed between the semiconductor substrate and the third semiconductor layer, a top surface of the third semiconductor layer being higher than a top surface of the second semiconductor layer in the second region.
A method for fabricating a semiconductor device according to an aspect of the present invention comprises:
forming a first insulation film, a first semiconductor layer, and a second insulation film in sequence in first to third regions of a semiconductor substrate;
removing the first insulation film, the first semiconductor layer, and the second insulation film in the first region and the second insulation film in the third region;
selectively forming a second semiconductor layer in the first region of the semiconductor substrate and on the first semiconductor layer in the third region; and
removing the second insulation film.